Emulation systems may comprise hardware components, such as emulation chips and processors, capable of processor-based (i.e., hardware-based) emulation of logic systems, such as application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPU), and the like. By executing various forms of programmable logic, the emulation chips may be programmed to mimic the functionality of nearly any prototype logic system design that is undergoing testing. This allows logic system designers to prototype their ASIC or other logic system design using processor-based emulation before expending resources manufacturing the ASIC or other logic system product.
In conventional approaches, when compiling a netlist into virtual logic the compiler produces holes in the instruction sets. That is, for each hole, there is an invalid instruction or meaningless instruction placed at that particular location in an instruction memory. Conventional approaches to multiphase execution merely allow the compiler to make multiple passes at compilation, and may allow the system to execute the instruction sets multiple times. However, what is needed for greater efficiency and more processing power is the ability to select or generate different inputs or outputs based on the phase.